1. Field of the Invention
This invention relates to the fabrication of semiconductor devices and more specifically, to a new method for annealing and well drive of an implanted well in a CMOS device on a bare silicon wafer.
2. Description of Related Art
Semiconductor manufacturing technology has advanced to the point where a single die may contain millions of active devices. Illustrative of this advancement is the fact that since the late 1960""s there has been over a two-hundred-fold increase in functional density, and twenty-fold increase in speed of integrated circuits. In light of the direction and demands of semiconductor manufacturing CMOS is now the dominant integrated circuit technology.
In CMOS fabrication the silicon wafers are subjected to many elevated temperature steps in order to effect a variety of changes in the material properties of the wafer and fabricated device. One of the high temperature processes used in CMOS technology is ion implantation to drive in the wells used in the devices. Ion implantation has many advantages including more precise control of the number of impurity atoms introduced into the wafer substrate. Unfortunately ion implantation cannot be achieved without damage to the material structure of the target substrate.
Defects in the silicon substrate impact important functional parameters which can cause device failures by excessive leakage currents, etc. To restore the target material to its pre-ion-implantation condition, additional processing must be performed on the wafer. Each additional process step that is required subjects the wafer to an additional source of stress and potentially introduces new insults and injuries to the wafer and fabricated device. As the functional density and speed of integrated circuits increases, there is less ability for the wafers to tolerate functional imperfections introduced during fabrication and manufacture and still operate.
What is still needed is improved fabrication processes that allow better control of the stresses and exposures to a silicon substrate and reduces the total number of process steps required.
It is an object of the present invention to provide a CMOS well-drive process that allows annealing and denuding of the wafer at the same time It is another object to provide a better denuding zone and reduced silicon pitting.
It is a further object to provide a CMOS well-drive process that puts the silicon wafer in better condition for subsequent fabrication steps than the existing well-drive processes.
The present invention is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.
One exemplary embodiment of the current invention concerns a method for denuding, annealing and well drive of an implanted well in CMOS fabrication on a bare silicon wafer comprising:
heating the wafer to a high temperature in the range from about 500xc2x0 to 700xc2x0 C. in an argon ambient environment;
annealing and driving the well into the wafer in an argon/hydrogen ambient environment under high temperature in the range from about 1100xc2x0 to 1250xc2x0 C.; and
oxidizing the wafer under high temperature in the range from about 800xc2x0 to 1100xc2x0 C.
In a more specific exemplary embodiment, the argon/hydrogen ambient environment contains between 0.5 to 10% hydrogen.
In another more specific exemplary embodiment, the wafer is held at the desired temperature for a period of at least 10 hours during the step of oxidizing the wafer under high temperature.
In yet another more specific exemplary embodiment, the wafer is oxidized in an argon/oxygen ambient containing 1-20% oxygen.
One alternative exemplary embodiment comprises oxidizing the wafer under high temperature in the range from about 800xc2x0 to 1100xc2x0 C.
Additional objects, advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.